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AN1076/0199 1/12 application note st9+ external memory interface configuration by microcontroller division applications 1 introduction this application note presents the different st9+ resources for configuring and initializing its external memory interface. the st9+ has a single 4 mbyte memory space segmented in 64 segments of 64 kbytes, plus an independent register file space. the memory space contains internal memories (internal rom and ram with predefined addresses) and you can map your external memories (at the addresses in any segments not used for internal memories). please refer to the mmu chapter of the st9+ datasheet for more information on the way this memory space is addressed. the st9+ external memory access cycle is composed of 2 clock phases (cf. figure 1): C phase t1: the memory address is output through the st9+ emi (external memory interface). C phase t2: if the memory access is a read cycle, the data signals are sampled by the st9+. if the memory access is a write cycle, the st9+ outputs data to be written in external mem- ory. the different signals provided and used by the emi are described in section 2 of this applica- tion note, and their configuration is explained in section 3. a software example of the st9+ emi configuration is given in the section 4. 2 signal description the external memory interface for the st9+ microcontroller exists in two models: a small model that allows you to address a maximum of 64 kbytes of external memory and the large model which can address the full st9+ memory space (4 mbytes). 2.1 small memory model in this model, the st9+ is limited to a maximum of 64 kbytes of directly addressable external memory. it is due to the fact that you can only output 16-bit addresses, which corresponds to a 64 kbyte external memory space. 1
st9+ external memory interface configuration 2/12 the signals used in the small memory model interface are the following: C i/o port 0 (8 pins): outputs the lsb of the address (a[0..7]) multiplexed with the 8 bits of data (d[0..7]). C i/o port 1 (8 pins): outputs the msb of the address (a[8..15]). C address strobe asn: is active during clock phase t1. an asn rising edge indicates that the memory address and control signals are valid. C data strobe dsn: is active during clock phase t2. during an external memory read cycle, the data on port 0 must be valid before the rising edge of dsn. during an external memory write cycle, the data on port 0 are output on the falling edge of dsn and they are valid on the rising edge of dsn. C read/write rwn: identifies the type of memory cycle. rwn=1 identifies a read cycle and rwn=0 identifies a write cycle. if you want to access more than 64 kbytes of memory with this interface, you will have to use some i/o pins as chip select signals for your external memories and handle the management of these pins by software. figure 1. external memory read/write with and without a programmable wait n as stretch ds stretch address address address address data in data in data out data t1 t2 t1 t2 no wait cycle 1 asn wait cycle 1 dsn wait cycle always read write asn p1 dsn p0 rwn p0 rwn address address cpu clock internal clock
3/12 st9+ external memory interface configuration 2.2 large memory model in this model, you can address all the st9+ memory space (4mbytes), using a 22-bit address bus output on the st9+ ports. the signals used in the large memory model interface are the following: C i/o port 0 (8 pins): same function as small memory model (a[0..7]/d[0..7]). C i/o port 1 (8 pins): same function as small memory model (a[8..15]). C i/o port 2 (6 pins): outputs the mmu bits of the address (a[16..21]). C i/o port 6 (8 pins): if the non-multiplexed bus option is chosen (refer to section 3.2), it outputs the lsb of the address (a[0..7]). in this case, port 0 only outputs the 8 bits of data (d[0..7]). C address strobe asn: same function as small memory model. C data strobe dsn: same function as small memory model. C data strobe 2 ds2n: if enabled, this pin can be used as a second data strobe. in this case, dsn addresses the external upper memory block while ds2n addresses the external lower memory block. the upper memory is located at addresses >200000h (a21=1, typically ram), and the lower memory is located at addresses <200000h (a21=0, typically rom). C read/write rwn: same function as small memory model.
st9+ external memory interface configuration 4/12 3 external memory interface configuration the external memory interface configuration consists of port configuration, mode configura- tion, timing configuration, and mmu (memory management unit) configuration. these dif- ferent types of initialization are presented in the following paragraphs. figure 2 shows the mapping of the different registers which are referred to in this chapter. figure 2. register map moreover, the wcr register is mapped to r252 (fch) in register page 0 in group f. the register map described above is the default setting. if the dprrem bit in the emr1 reg- ister is set, the mapping of registers p0dr, p1dr, p2dr, and p3dr is exchanged with that of dpr0, dpr1, dpr2, and dpr3. group e group f page 21 group f page 2 group f page 3 ffh reserved p7dr r255 feh p3c2 p7c2 r254 fdh p3c1 p7c1 r253 fch p3c0 p7c0 r252 ebh moder r235 fbh reserved p6dr r251 fah p2c2 p6c2 r250 f9h dmasr p2c1 p6c1 r249 f8h isr p2c0 p6c0 r248 f7h reserved reserved r247 f6h emr2 p1c2 p5c2 r246 e5h p5dr r229 f5h emr1 p1c1 p5c1 r245 e4h p4dr r228 f4h csr p1c0 p5c0 r244 e3h p3dr r227 f3h dpr3 reserved reserved r243 e2h p2dr r226 f2h dpr2 p0c2 p4c2 r242 e1h p1dr r225 f1h dpr1 p0c1 p4c1 r241 e0h p0dr r224 f0h dpr0 p0c0 p4c0 r240
5/12 st9+ external memory interface configuration 3.1 port configuration the different ports used to interface with the external memory must be configured as alternate function output push-pull. this concerns ports 0,1 and optionally ports 2 and 6 for the large memory model. this configuration is done by writing the following values in the three i/o port configuration reg- isters: C pxc2 = 00h C pxc1 = ffh C pxc0 = ffh (where x is the number of the corresponding i/o port). after reset, if your microcontroller is a romless version, this configuration will be the default one. in this case, the microcontroller must directly address external memory just after the reset, as there is no internal memory. for other microcontroller versions (not romless), the reset configuration for the i/o ports is usually bidirectional open-drain weak pull-up (refer to your device datasheet for special i/o ports reset configuration). in this case, you have to initialize the three i/o port configuration registers by software as shown above, before being able to address external memory. you also have to configure the other external memory interface signals. for example, to con- figure the rwn signal for the st90158 microcontroller, you must select the alternate function push-pull for the p6.5 pin.
st9+ external memory interface configuration 6/12 3.2 mode configuration the various modes of the external memory interface are configured through the bits of the emr1 and moder control registers. n emr1 register: C mode control (mc bit 6): by setting this bit, the intel mode is used for the external memory interface. in this mode, the asn pin becomes ale (address load enable), which corre- sponds to asn inverted. the dsn pin becomes oen (output enable), which behaves like dsn during a read cycle, but which is forced to 1 during write cycles. the rwn pin be- comes wen (write enable), which behaves like dsn during a write cycle, but which is forced to 1 during read cycles. C buffer size (bsz bit 1): when this bit is 0 (default value), the external memory interface pins use smaller, less noisy output buffers. this may limit the operation frequency of the device. typically, for an internal frequency greater than 10mhz, this bit must be set to use larger (but more noisy) buffers. another possibility is to add some wait states to slow down the external memory interface signals (see section 3.4). C data strobe 2 enable (ds2en bit 5): large memory model option. setting this bit enables the second address strobe pin ds2n. in this case, dsn is used when the upper memory block is addressed (while ds2n is forced to 1), and ds2n is used when the lower memory block is addressed (while dsn is forced to 1). C non-multiplexed bus (nmb bit 3): large memory model option. when this bit is zero, port 0 outputs the multiplexed data and the lsb of the address. when this bit is 1, it is port 6 which outputs the address lsb (port 0 is released in high impedance during this time), and port 0 only outputs data. n moder register: C high impedance (himp bit 0): setting this bit forces the external memory interface signals (ports 0, 1, 2, 6 and asn, dsn, rwn) into high impedance state. this option is recom- mended for program phases where only internal memory is used, in order to reduce noise. this bit must be kept to zero when the external memory has to be accessed (permanently for a romless version). n emr2 register warning : the bit 4 of the emr2 register must be set by the user when using the external memory inter- face. be very careful with this bit because the reset value is 0 in some devices.
7/12 st9+ external memory interface configuration 3.3 hardware implementation examples depending on the mode configuration (and the availability for your device), the hardware im- plementation can be different. for a small memory model, you will have to use a latch connected to the multiplexed address/ data bus. the figure below shows an example of this (figure 3). figure 3. small memory model example n for a st9+ microcontroller with the large external memory interface model, you can benefit from the possibilities of the extended mode configuration. the following figure (figure 4) shows an example for a large memory model, where the non- multiplexed bus (nmb bit of the emr1 register) and the second data strobe (ds2en bit of the emr1 register) options have been chosen. this allows some external hardware devices like the latch to be saved. ram 64 kbytes g e a0-a15 a15-a8 st9+ dsn p1 q0-q7 p0 w rwn d1-d8 asn oe le q1-q8 a0-a7/d0-d7 latch
st9+ external memory interface configuration 8/12 figure 4. large memory model example n rom 512 kbytes ram 64 kbytes g e e q0-q7 a0-a15 a7-a0 a15-a8 a20-a16 a21 a0-a18 dq0-dq7 g w st9+ rwn dsn p0 ds2n p2 p1 p6
9/12 st9+ external memory interface configuration 3.4 timing configuration all the different signals of the external memory interface are driven by the cpu clock (cpuclk). the cpu clock is the result of the internal clock (intclk) divided by a prescaler. please refer to the rccu (reset and clock control unit) chapter of the st9+ datasheet for further details on the clock. if your external memory is too slow to follow the st9+ frequency, you can slow down the ex- ternal memory interface signals in different ways: C reducing only the cpuclk frequency (through the moder register). C adding wait states on the asn and dsn signals (through emr2 and wcr registers). C adding wait cycles through the waitn external pin. n moder register: the three bits prs0, prs1, prs2 load the prescaler division factor for the internal clock (intclk which feeds the peripherals). the resulting signal is the cpu clock which drives the external memory interface signals. you can divide the frequency by a factor from 1 to 8, but this slow down will also affect all the code execution, as the cpu clock feeds the core. n emr2 register: this register contains the control bits used to add wait states on the address strobe asn signal. two bits (las[1:0]) contains the number of clock cycles to add to the cpulck to stretch asn during external lower memory block accesses, whereas two other bits (uas[1:0]) have the same action for external upper memory block accesses. you can add from 0 to 3 wait states to the asn signal. refer to figure 1 to see the effect of these wait states on the various signals. n wcr register: this register contains the control bits used to add wait states on the data strobe dsn signal. three bits (lds[2:0]) are used for the lower memory block accesses and three other bits (uds[2:0]) are used for the upper memory block accesses. you can add from 0 to 7 wait states to the dsn signal. refer to figure 1 to see the effect of these wait states on the various signals. n waitn external pin: you can also add wait states using the waitn external pin which indicates to the st9+ that the external memory requires more time to complete the memory access cycle. this function is enabled if the ewen bit of the eivr register is set. this pin is sampled on each rising edge of the internal clock: if waitn is active (active low), one clock cycle is added to the memory cycle. on the following rising edge of the clock, waitn is sampled again to continue or finish the memory cycle stretching. if waitn is sampled active
st9+ external memory interface configuration 10/12 during phase t1 then asn is stretched, while if waitn is sampled active during phase t2 then dsn is stretched. n tips: C the wait cycles added on the clock always refer to the internal clock (intclk) and not to the cpuclk. it means that if you choose 3 wait states for example, there will be three intclk clock cycles added to the cpu clock (cpuclk). during the wait states, the cpu- clk will remain high for the number of periods of intclk corresponding to the number of wait states programmed (3 in this example). C be careful of the reset values of the control bits in the registers emr2 and wcr (las, uas, lds, uds). by default, the maximum number of wait states is inserted. so, if your memory can work faster, you must remember to change the value of these bits to increase the speed of the st9+ external memory interface. 3.5 mmu configuration you will also have to configure your memory management unit to access your external memory. this will be exactly the same as when you configure your internal memory: C you have to load the correct value in the mmu registers in order to point to your correspond- ing external memory pages or segments (dpr0, dpr1, dpr2, dpr3, csr, isr, dmasr registers). C you have to add your external memory description and mapping in your scriptfile. you will optionally have to use the .bk9 sections if needed. C dont forget to describe your external memory also in the emulator configuration file hard- ware.gdb. please refer to the st9+ microcontroller datasheet, to the gnu c compiler user manual, and to the emulator user manual for further details on these configurations.
11/12 st9+ external memory interface configuration 4 software example the code below shows a software example of a small memory model interface (st90158 mi- crocontroller example) with an external memory located in segment 1 of the memory (and pointed to by dpr0, dpr1, and dpr2. dpr3 points to the internal ram in segment 20h). spp #21 ld r245, #082h ;emr1 register: normal mode & high-speed buffers ld r246, #050h; ;emr2 register: zero wait states & (bit 4)=1 spp #0 ld r252, #40h ; wcr: zero wait states ld r235, #20h ; moder: no prescaler division & no high impedance spp #3 ld r250,#000h ;p6.5 in alternate function ld r249,#0ffh ; push-pull ld r248,#0ffh ; (rw pin) spp #2 ld r242,#000h ;port 0 in alternate function ld r241,#0ffh ; push-pull ld r240,#0ffh ; (address lsb/data multiplexed) ld r246,#000h ;port 1 in alternate function ld r245,#0ffh ; push-pull ld r244,#0ffh ; (address msb) spp #21 ld r240, #0x04 ;dpr0 register ld r241, #0x05 ;dpr1 register ld r242, #0x06 ;dpr2 register ld r243, #0x83 ;dpr3 register sdm ; set data memory ld 0x0000,#0xaa ;examples of data transfers ld 0x4000,#0xaa ; in external memory ld 0x8000,#0xaa ;
st9+ external memory interface configuration 12/12 "the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connexion with their products." information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

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